fdhwlib
2.0.25
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00001 /*************************************************************************** 00002 sltdef.h - base defines for v4 slt 00003 00004 begin : Tue Jul 18 2000 00005 copyright : (C) 2000 by Andreas Kopmann 00006 email : kopmann@hpe.fzk.de 00007 ***************************************************************************/ 00008 00009 #ifndef _HW4_SLTDEF_H_INCLUDED 00010 #define _HW4_SLTDEF_H_INCLUDED 00011 00012 // USCT 00013 #ifdef USCT 00014 # define SLT_VER 110 00015 #endif // USCT 00016 00017 // V4 00018 #ifdef V4 00019 # define SLT_VER 400 00020 #endif // V4 00021 00022 #ifndef SLT_VER 00023 // Version of the SLT description 00024 // 1.00 First version 00025 //# define SLT_VER 100 00026 // 1.10 Minor modification effecting the control register 00027 // Released 7.6.01 ak 00028 //# define SLT_VER 110 00029 // 3.00 Changes for Hardware version 3 00030 // Numbering of the slots changed 00031 // Memory doubled 00032 //# define SLT_VER 300 00033 // 3.10 New: veto time counters and 00034 // the trigger time stamp information changed 00035 //# define SLT_VER 310 00036 // 4.00 Driver for Hw Version 4 00037 # define SLT_VER 400 00038 #endif // SLT_VER 00039 00040 00041 // Version number of the slt implementation 00042 00043 #define SLT_HW_VER400 0x40 // 2009-07-17 the first v4 version number 00044 00045 00046 // AM to Versions 3.11 to 3.13 00047 // I downloaded today new slt revision with number 0x1c in Co. 00048 // In the previous two revisions I implemented 00049 // in the control register bit 16. This bit I used during my 00050 // tests of the single phe measurements (this bit when '1' masks 00051 // external inhibit). To avoid any possible troubles during 00052 // DAQ tests I cancelled this bit. It still can be written and 00053 // read back but it has no influence on the slt behaviour. 00054 00055 00056 #define SLT_HW_VER35 0x23 // ??? 00057 #define SLT_HW_VER34 0x22 // ??? 00058 #define SLT_HW_VER318 0x21 // Mar 2006 no reset release after startup required (for FLTs) 00059 #define SLT_HW_VER317 0x20 // Mar 2005 changes/ fixes of dead/veto counter?! 00060 #define SLT_HW_VER316 0x1f // Oct 2004, Bug fixes in page controller 00061 // Changed order of dead time counters 00062 // Status of setpagefree: reading register will give 00063 // 1 if still running, 0 if ready...(?) 00064 #define SLT_HW_VER315 0x1e // Mar 2004, Improved timing in Slt-FPGA design 00065 // Fixed problems: Disfunction after burn-in tests 00066 // Second strobe not recocnised after a while 00067 #define SLT_HW_VER314 0x1d // ??? 00068 #define SLT_HW_VER313 0x1c // Feb 2004, Ext Inhibit Mask disabled again 00069 #define SLT_HW_VER312 0x1b // Nov 2003 00070 #define SLT_HW_VER311 0x1a 00071 #define SLT_HW_VER310 0x19 00072 00073 #define SLT_HW_VER300 0x18 00074 #define SLT_HW_VER110 0x02 // ??? 00075 #define SLT_HW_VER100 0x00 00076 00077 // Define for which version the library can be used 00078 // Give min and max value that is compatible 00079 00080 #if defined (SLT_VER) && (SLT_VER >= 400) 00081 # define SLT_HW_VER SLT_HW_VER400 00082 # define SLT_HW_VER_MAX SLT_HW_VER400 00083 #endif // SLT_VER 400 00084 00085 // Number of memory pages 00086 #define SLT_PAGES 64 00087 00088 // Flags of the IR mask 00089 //#define SLT_IRMASK_NXPG 0x01 00090 //#define SLT_IRMASK_PG_ERR 0x02 00091 //#define SLT_IRMASK_FLT_CONF_ERR 0x04 00092 //#define SLT_IRMASK_CONF_ERR 0x08 00093 //#define SLT_IRMASK_SLOW_CNTRL_ERR 0x10 00094 00095 //#define SLT_IRMASK_C_SYNC_ERR 0x20 00096 //#define SLT_IRMASK_T_SYNC_ERR 0x40 00097 //#define SLT_IRMASK_SYNC_ERR 0x60 00098 00099 #if defined (SLT_VER) && (SLT_VER >= 400) 00100 // Trigger sources 00101 # define SLT_TRIGGER_SW 0x01 // Software 00102 # define SLT_TRIGGER_I_N 0x07 // Internal + Neighbors 00103 # define SLT_TRIGGER_LEFT 0x04 // left neighbor 00104 # define SLT_TRIGGER_RIGHT 0x02 // right neighbor 00105 # define SLT_TRIGGER_INT 0x08 // Internal only 00106 # define SLT_TRIGGER_EXT 0x10 // External 00107 # define SLT_TRIGGER_FRN 0x20 // Front Panel 00108 00109 // Inhibit masks 00110 # define SLT_INHIBIT_SW 0x01 // Software 00111 # define SLT_INHIBIT_INT 0x02 // Internal 00112 # define SLT_INHIBIT_EXT 0x04 // External 00113 # define SLT_INHIBIT_ALL 0x07 // Internal + External 00114 # define SLT_INHIBIT_NO 0x01 // None of both (only Software) 00115 00116 // Test pulse settings ??? 00117 //#define SLT_TESTPULS_NO 0x00 // None 00118 //#define SLT_TESTPULS_EXT 0x02 // External 00119 //#define SLT_TESTPULS_SW 0x01 // Software 00120 00121 // Second strobe sources 00122 # define SLT_SECSTROBE_INT 0x00 // Internal SecStrobe Signal 00123 # define SLT_SECSTROBE_EXT 0x01 // Extern 00124 00125 #endif // SLT_VER >= 400 00126 00127 #if 0 // thjm 00128 /* Mask for the IR controller on the Slt board: 00129 * The interrupt "NextPage" is generated if a next page 00130 * signal occures. 00131 */ 00132 #define SLT_IRMASK_NXPG 0x0001 00133 00134 /* Mask for the IR controller on the Slt board: 00135 * The interrupt "Warning AllPagesFull" is 00136 * generated if the actual page 00137 * pointer is set to the last free page. The 00138 * next trigger will stop the data aquisition. 00139 */ 00140 #define SLT_IRMASK_WAR_PGFULL 0x0002 00141 00142 /* Mask for the IR controller on the Slt board: 00143 * The interrupt "Error Loading Flt FPGAs" 00144 * is generated if an error 00145 * occures while the configuration of the 00146 * FPGAs on the Flt boards. 00147 */ 00148 #define SLT_IRMASK_ERR_FLT 0x0004 00149 00150 /* Mask for the IR controller on the Slt board: 00151 * The interrupt "Error Configuration" 00152 * is generated if the command 00153 * configure FPGAs is given on a system without 00154 * an confuration error?! 00155 */ 00156 #define SLT_IRMASK_ERR_CONF 0x0008 00157 00158 /* Mask for the IR controller on the Slt board: 00159 * The interrupt "Error Sensor OutOfRange" is generated if one 00160 * of the sensors leaves the allowed range. 00161 */ 00162 #define SLT_IRMASK_ERR_SC 0x0010 00163 00164 /* ? 00165 */ 00166 #define SLT_IRMASK_ERR_CFPGA 0x0020 00167 /* ? 00168 */ 00169 #define SLT_IRMASK_ERR_TFPGA 0x0040 00170 00171 00172 /* Mask for the IR controller on the Slt board: 00173 * The interrupt "Error PageFull" is generated if all pages 00174 * are full. The data aquisition has been stopped 00175 * in this case and needs to be restarted 00176 * manually after some pages have been cleared. 00177 */ 00178 #define SLT_IRMASK_ERR_PGFULL 0x0080 00179 00180 /* Mask for the IR controller on the Slt board: 00181 * The interrupt "PageLost" is generated if an next 00182 * page occures before an acknowledge for 00183 * last occurence of the trigger has been received. 00184 * If this warning occures, it is necessary 00185 * to analyse the page status register for 00186 * the filled pages. At least one page number will not 00187 * be returned with the acknoledge vector. 00188 */ 00189 #define SLT_IRMASK_WAR_PGLOST 0x0100 00190 00191 00192 /* Mask for the IR controller on the Slt board: 00193 * An interrupt is generated if at least one 00194 * of the two FPGA errors occure. 00195 * In both cases the synchronisation with the 00196 * second strobe signal failed. 00197 * This mask includes Error CFPGA Sync and 00198 * Error TFPGA Sync 00199 */ 00200 #define SLT_IRMASK_ERR_SYNC 0x0060 00201 00202 00203 /* Mask for the IR controller on the Slt board: 00204 * An interrupt is generated if any of 00205 * the page controller interrupts is generated. 00206 * This mask includes "NextPage", "Warning AllPagesFull", 00207 * "Error AllPagesFull" and "Warning PageLost". 00208 * 00209 */ 00210 #define SLT_IRMASK_PGCTRL 0x0183 00211 00212 #endif // thjm 00213 00214 // new constants for V4, I prefer them to be in a namespace 00215 00216 namespace hw4 { 00217 00219 static const int kSLT_VER = SLT_VER; 00220 00222 static const int kSLT_PAGES = 64 /* SLT_PAGES */; 00223 00225 static const int kSLT_SAMPLES = 2000; 00226 00228 static const int kMULTIPLICITY_SAMPLES = 1000; 00229 00231 static const int kSLT_COINCTIME_STEPWIDTH = 30; 00232 00234 static const int kSLT_TRIGGERWINDOW_MAX = 7; 00235 00236 } // namespace hw4 00237 00238 #endif // _HW4_SLTDEF_H_INCLUDED