Register and Register Items

The basic element for control and data readout is the register object.

The board classes implement all registers using the register specific register classes. Additionally all registers of a board are collected in a a list. The list can be used to display all defined information for a certain FPGA design. The register list allows all operation of the class BaseRegister although in the specific register classes more functions might be implemented. These special functions are avaialble only using the direct register instance and not the general reference in the register list.

The register object can be used for different control objects in the FPGA implementation.

• Single registers occure once per board and have a 32bit length.
• Register groups are two or more single registers that use a continuous address range. This is used to form 64bit counters or the summarize timestamp and other event information. In this case the length of the register group is 64bit longer but it still occures only once per board.
• Register vectors are groups of registers of the same type. These registers normally do not use a contiuous address range. Each element of the register vector can be access individually using a additional element number.

For each register a number of register items is defined. Especially status and control registers contain several flags and control bits. All register items are summarized in a item list. The register list together with the item list define a hierarchical structure that allows to control all features of the FPGA design. A user interface can display the names of all objects to generate configuration and maintanance dialogs. In this way the interface library provides both: A generic interface with function names as parameter and one based on the functions implemented as obejct oriented class members.

The register object is the entity that provide access to the hardware. Each read or write access communicated with the electronics. The results of the last read access are store in a class internal cache. With the special cache operation the cache can be access for later analysis. The cache can also be used to asemble a desired bit sequence using the standard implementation.

Read the items of a status register:

// Read the data to the class cache
theSlt->status->read();

// Use the cache to get status bits of the last read-access 
inhibit = theSlt->status->inhibit->isActive()
powerFail = theSlt->status->vttError->isActive()

Assemble a command string:

// Assemble the bit sequence 
// Warning: It is necessary to clear the cache before
theSlt->command->setCache(0);
theSlt->command->clearInhibit->setCache(1);
theSlt->command->clearCounter->setCache(1);

// Write the cache to the electronics
theSlt->command->writeCache();